1. Field
Aspects of the present disclosure relate to semiconductor devices, and more particularly to isolation between adjacent devices.
2. Background
As integrated circuit (IC) technology advances, device geometries are reduced. Reducing the geometry and “pitch” (spacing) between devices may cause devices to interfere with each other in terms of proper operation.
Fin-based devices are three-dimensional structures on the surface of a semiconductor substrate. A fin-based transistor, which may be a fin-based metal-oxide-semiconductor field-effect transistor (MOSFET), may be referred to as a FinFET. A nanowire field-effect transistor (FET) is also a three-dimensional structure on the surface of a semiconductor substrate. A nanowire FET includes doped portions of the nanowire that contact a channel region and serve as the source and drain regions of the device. A nanowire FET is also an example of a MOSFET device.
The performance of MOSFET devices can be affected by numerous factors including channel length, strain and external resistance. One substantial factor that contributes to the performance of MOSFET devices is interference between adjacent devices. Interference between adjacent devices is a device performance and scaling limiter for advanced technology nodes in which the geometry and pitch between devices is dramatically reduced.